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Fun with Threshold Logic Gates

April 25, 2012 Leave a comment

Dammit, I tried writing the best darn paper I could in hopes of scoring a free trip to Vegas on university money, but costs a lot of money to have you paper submitted to the conference being held there. Oh well, I guess I ended up learning something, if that’s worth anything.

So the class project I did was to make a 4-bit full adder using threshold gates and written in Verilog HDL so it can be loaded onto an FPGA. A threshold gate is sort of a model of a neuron cell from the brain. Basically, the binary inputs (1 or 0) are multiplied by individual weights (positive or negative integers) and summed. Then the gate output is “1” if the sum is greater than a threshold value, or “0” is less. The benefit of this is the ability to reduce a complex Boolean function to one gate (certain restrictions apply). To find the weights and threshold value Dertouzos’ method is used, which surprisingly was not googleable.

Threshold Gate

Even if a function can’t be reduced to a single gate, multiple threshold gates can be connected together to form a neural network or cascaded to still be realized. The sum function for a full adder can’t be realized as one, but the carry out can be. Luckily another method, called IMS (Implied Minterm Structure), does the trick and groups the minterms so Dertouzos’ method works. Using IMS, three threshold gates are needed to cover the sum minterms and then connected together with a forth.

Threshold gates for Full Adder

Now that the number crunching is done, its time to code this into Verilog. Supposedly real numbers can be used, but the old version in the lab couldn’t, so I had to settle for integers. To get the code to compile, all of the threshold values needed to be rounded up and then the threshold inequality needs to be changed to greater or equal. Since each threshold gate has a different combo of weights and threshold, each one was written separately, then combined as a full adder module and finally into a 4-bit full adder. It even worked when loaded into an FPGA (Spartan variety). Below is the code so you can claim it as original for you’re next class project or perhaps for some nerdy shits and giggles.

module threshold1(f, A, B, C);
    output f;
    input A,B,C;
    reg f;

    parameter integer w1 = 1, w2 = 1, w3 = 1, t = 1;
    integer out;

    always@(A or B or C)
    begin
    out = A*w1 + B*w2 + C*w3;
        if (out >= t)
            f = 1'b1;
        else
            f = 1'b0;

    end
endmodule

module threshold2(f, A, B, C);
    output f;
    input A,B,C;
    reg f;

    parameter integer w1 = 1, w2 = 1, w3 = 1, t = 2;
    integer out;

    always@(A or B or C)
    begin
    out = A*w1 + B*w2 + C*w3;
        if (out >= t)
            f = 1'b1;
        else
            f = 1'b0;

    end
endmodule

module threshold3(f, A, B, C);
    output f;
    input A,B,C;
    reg f;

    parameter integer w1 = 1, w2 = 1, w3 = 1, t = 3;
    integer out;

    always@(A or B or C)
    begin
    out = A*w1 + B*w2 + C*w3;
        if (out >= t)
            f = 1'b1;
        else
            f = 1'b0;

    end
endmodule

module threshold4(f, A, B, C);
    output f;
    input A,B,C;
    reg f;

    parameter integer w1 = 1, w2 = -1, w3 = 1, t = 1;
    integer out;

    always@(A or B or C)
    begin
    out = A*w1 + B*w2 + C*w3;
        if (out >= t)
            f = 1'b1;
        else
            f = 1'b0;

    end
endmodule

module threshold5(f, A, B, C);
    output f;
    input A,B,C;
    reg f;

    parameter integer w1 = 1, w2 = 1, w3 = 1, t = 2;
    integer out;

    always@(A or B or C)
    begin
    out = A*w1 + B*w2 + C*w3;
        if (out >= t)
            f = 1'b1;
        else
            f = 1'b0;

    end
endmodule

module fulladder (sum, c_out, A, B, c_in);
    output sum, c_out;
    input A, B, c_in;
    wire x, y, z;

    threshold1 n1 (x, A, B, c_in);
    threshold2 n2 (y, A, B, c_in);
    threshold3 n3 (z, A, B, c_in);
    threshold4 n4 (sum, x, y, z);

    threshold5 n5 (c_out, A, B, c_in);

endmodule

module full_4bit_adder (sum, c_out, A, B, c_in);
    output [3:0] sum;
    output c_out;
    input [3:0] A;
    input [3:0] B;
    input c_in;
    wire x, y, z;

    fulladder a1 (sum[0], x, A[0], B[0], c_in);
    fulladder a2 (sum[1], y, A[1], B[1], x);
    fulladder a3 (sum[2], z, A[2], B[2], y);
    fulladder a4 (sum[3], c_out, A[3], B[3], z);

endmodule
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